1. Field of the Invention
The invention relates to a semiconductor device having dynamic memory, such as a DRAM device. More particularly, the invention relates to such a semiconductor device that includes a self refresh test mode in which self refresh is monitored and/or modified by an external testing device. The invention also includes a method for constructing such a semiconductor device.
2. State of the Art
DRAMS (dynamic random access memory) include numerous cells in which data are stored. Such cells may include capacitive elements to which a charge is applied to signify a high or low voltage. However, because of leakage, the voltage of the charge decreases over time, making the contents of the cells unreliable. Refresh involves reading a datum from a cell before the datum becomes corrupted and rewriting the datum into the cell. The read and rewriting process may be essentially simultaneous.
There are various types of DRAM devices and various types of refresh. DRAMs are often referred to as either “standard refresh” or “extended refresh.” Whether a DRAM is a standard refresh or an extended refresh device may be determined by dividing the specified refresh time by the number of cycles. Table 1 lists some of the standard DRAMs that have been marketed by Micron Technology, Inc., assignee of the present invention, and their refresh specifications:
DRAMREFRESH TIMENO. OF CYCLESREFRESH RATE4 Meg× 116ms1,02415.6μs256K× 168ms51215.6μs256K× 1664ms512125μs(L Version)4 Meg× 432ms2,04815.6μs(2K)4 Meg× 464ms4,09615.6μs(4K)DRAMs having refresh rates of 15.6 μs are standard refresh devices, while DRAMs having refresh rates of substantially greater than 15.6 μs/row are extended refresh devices.
Two basic means of performing refresh are distributed and burst refresh. Distributing the refresh cycles so that they are evenly spaced is known as distributed refresh. When not being refreshed, the DRAM may be read from or written to. In distributed refresh, the DRAM controller is set up to perform a refresh cycle, for example, every 15.6 μs. Usually, this means the controller allows the current cycle to be completed, and then holds off all instructions while a refresh is performed on the DRAM. The requested cycle is then allowed to resume. Refresh may be achieved in a burst method by performing a series of refresh cycles, one right after the other until all rows have been accessed. During refresh, other commands are not allowed.
Different cycles may be used to refresh DRAMs, all of which may be used in a distributed or burst method. Standard refresh types include (1) {overscore (R)}Ā{overscore (S)}-ONLY refresh, (2) {overscore (C)}Ā{overscore (S)}-BEFORE-{overscore (R)}Ā{overscore (S)} (CBR) refresh, and (3) Hidden refresh. To perform a {overscore (R)}Ā{overscore (S)}-ONLY refresh, a row address is put on the address lines and then {overscore (R)}Ā{overscore (S)} is dropped. When {overscore (R)}Ā{overscore (S)} falls, that row will be refreshed and, as long as {overscore (C)}Ā{overscore (S)} is held high, the DQs will remain open.
The DRAM controller provides addresses of cells to be refreshed. The row order of refreshing does not matter as long as each row is refreshed in the specified amount of time.
A CBR refresh cycle is performed by dropping {overscore (C)}Ā{overscore (S)} and then dropping {overscore (R)}Ā{overscore (S)}. One refresh cycle will be performed each time {overscore (R)}Ā{overscore (S)} falls. {overscore (W)}Ē (write enable) is held high while {overscore (R)}Ā{overscore (S)} falls. The DQs will remain open during the cycle. In the case of CBR refresh, an internal counter is initialized to a random count when the DRAM device is powered up. Each time a CBR refresh is performed, the device refreshes a row based on the counter, and then the counter is incremented. When CBR refresh is performed again, the next row is refreshed and the counter is incremented. The counter will automatically wrap and continue when it reaches the end of its count. There is no way to reset the counter. Row addresses are not externally supplied or monitored. {overscore (C)}Ā{overscore (S)} is held low before and after {overscore (R)}Ā{overscore (S)} falls to meet tCSR and tCHR. {overscore (C)}Ā{overscore (S)} may stay low and only {overscore (R)}Ā{overscore (S)} toggles. Every time {overscore (R)}Ā{overscore (S)} falls, a refresh cycle is performed. {overscore (C)}Ā{overscore (S)} may be toggled each time, but it is not necessary. The address buffers are powered-down because CBR refresh uses the internal counter and not an external address. For power sensitive applications, this may be a benefit, because there is no additional current used in switching address lines on a bus, nor will the DRAMs pull extra power if the address voltage is at an intermediate state. Because CBR refresh uses its own internal counter, there is not a concern about the controller having to supply the refresh addresses.
In Hidden refresh, the user does a READ or WRITE cycle and then, leaving {overscore (C)}Ā{overscore (S)} low, brings {overscore (R)}Ā{overscore (S)} high (for minimum of tRP) and then low. Since {overscore (C)}Ā{overscore (S)} was low before {overscore (R)}Ā{overscore (S)} went low, the part will execute a CBR refresh. In a READ cycle, the output data will remain valid during the CBR refresh. The refresh is “hidden” in the sense that data-out will stay on the lines while performing the function. READ and Hidden refresh cycles will take the same amount of time: tRC. The two cycles together take 2×tRC. A READ followed with a standard CBR refresh (instead of a Hidden refresh) would take the same amount of time: 2×tRC.
A self refresh mode helps maximize power savings in DRAMS and provide a very low-current data-retention mode. Low-power, extended-refresh DRAMs (LPDRAMs) have the same functionality as a standard DRAM, except they have been tested to meet the lower CMOS standby current and the extended refresh specifications. Self refresh DRAMs, on the other hand, require additional circuitry to be added to the standard DRAM to perform the self refresh function.
Self refresh mode provides the DRAM with the ability to refresh itself while in an extended standby mode (sleep or suspend). It is similar to the extended refresh mode of an LPDRAM except the self refresh DRAM utilizes an internally generated refresh clock while in the self refresh mode. During a system's suspend mode, the internally generated refresh clock on the DRAM replaces the DRAM controller refresh signals. Therefore, it is no longer necessary to power-up the DRAM controller while the system is in the suspend mode. Consulting the devices' data sheets will determine the power savings achieved.
Self refresh may employ parameters tRASS, tCHD and tRPS. The DRAM's self refresh mode is initiated by executing a {overscore (C)}Ā{overscore (S)}-BEFORE-{overscore (R)}Ā{overscore (S)} (CBR) refresh cycle and holding both {overscore (R)}Ā{overscore (S)} and {overscore (C)}Ā{overscore (S)} LOW for a specified period. The industry standard for this value is 100 μs minimum (tRASS). The DRAM will remain in the self refresh mode while {overscore (R)}Ā{overscore (S)} is LOW. Once {overscore (C)}Ā{overscore (S)} has been held LOW for tCHD, {overscore (C)}Ā{overscore (S)} is no longer required to remain LOW and becomes a “don't care.”
The self refresh mode is terminated by taking {overscore (R)}Ā{overscore (S)} HIGH for tRPS (the minimum time of an operation cycle). Once the self refresh mode has been terminated, the DRAM may be accessed normally.
Self refresh may be implemented in both a distributed method and a wait and burst method. In a system that utilizes distributed CBR refresh as the standard refresh, accesses to the DRAM may begin as soon as self refresh is exited. The first CBR pulse should occur immediately prior to active use of the DRAM to ensure data integrity. Since CBR refresh is commonly implemented as the standard refresh, this ability to access the DRAM immediately after exiting self refresh is a big benefit over the burst scheme described later. If anything other than CBR refresh is used as the standard refresh, a burst of all rows should be executed when exiting self refresh. This is because the CBR counter and the DRAM controller counter will not likely be at the same count. If the CBR counter and the DRAM controller counter are not at the same count and both are being used in the distributed method, then refresh will be violated and data will eventually be lost.
Self refresh may be implemented with an internal burst refresh scheme. Instead of turning on a row at regular intervals, a circuit would sense when the array needs to be refreshed and then sequence through the rows until all had been refreshed. When exiting a burst-type self refresh, the entire array must be refreshed before any accesses are allowed, regardless of the type of refresh used. This full burst is necessary because self refresh may have been exited just before the entire array was going to be refreshed. If the burst is not performed when exiting this type of self refresh, the refresh requirements may be violated, leading to lost data.
Some DRAMs allow access to the DRAM as soon as self refresh is exited, while other DRAMs may require a full burst when exiting, regardless of the refresh used. To prevent possible compatibility problems, the controllers are designed to perform the burst when existing self refresh.
FIG. 1 shows a functional block diagram for an exemplary prior art DRAM 10. It will be apparent to those skilled in the art that there are different types of DRAMs and that there is some flexibility in the choice of block diagrams to characterize the DRAM. It will also be apparent that, for clarity and simplicity, various components and conductors are not shown, but that an understanding of such components and conductors are within the knowledge of those skilled in the art. Accordingly, FIG. 1 is only exemplary. Referring to FIG. 1, data is written to or read from memory locations (or cells) of a memory array 14 through sense amplifier and input/output gating 18, data-in buffer 22 and data-out buffer 24. In ordinary operation, the address of a particular cell to be written to or read from is selected by a row decoder 28 and a column decoder 34 under the direction of addresses A0-A9, which are processed by row address buffers 38 and column address buffers 40. DRAM 10 may include a complement select and row select circuit between row decoder 28 and memory array 14.
A {overscore (R)}Ā{overscore (S)} signal is received by a clock generator 44, which, in response thereto, supplies the {overscore (R)}Ā{overscore (S)} signal to a refresh controller and self refresh oscillator and timer 64. Clock generator 44 also supplies clock signals to sense amp and input/output gating 18, row decoder 28, a clock generator 48. A {overscore (C)}Ā{overscore (S)} signal is supplied to control logic 56, a clock generator 48, column address buffers 40, and refresh controller and self refresh oscillator and timer 64. A write enable {overscore (W)}Ē signal and an output enable ŌĒ signal are also received by control logic 56. Control logic 56 controls data-in buffer 22 and data-out buffer 24 based on the state of {overscore (C)}Ā{overscore (S)}, {overscore (W)}{overscore (E )}, and ŌĒ, and a clock signal from clock generator 48, according to well-known protocols.
In self refresh mode, refresh controller and self refresh oscillator and timer 64 and a refresh counter 66 control the row address of the cell to be refreshed, while the column cells are refreshed simultaneously.
There may be difficulties in testing DRAM devices that incorporate a self refresh mode if the failures are present during self refresh operation. This complication may result because the external testing device no longer has control of internal DRAM clock signals such as {overscore (R)}Ā{overscore (S)} and {overscore (C)}Ā{overscore (S)}. Once the self refresh mode is entered, the DRAM internally times the necessary clock signals, and the external signals are ignored, except for external {overscore (R)}Ā{overscore (S)} which is used to terminate self refresh. A difficult test problem is encountered when a device failure occurs related to self refresh. In other failure modes, it is possible to vary timing to determine sensitivities of the failure to aid in troubleshooting the problem. In some cases, the failure is related to the period of the cycle the DRAM is in when self refresh is exited.
Prior systems have been proposed to provide signals indicative of the operations of a DRAM during self refresh. For example, U.S. Pat. No. 5,450,364 to Stephens, Jr. et al. describes a system the purpose of which is to create significant time savings in testing self refresh operation. The system is purported to generate a signal upon completion of the self refresh cycle, thus allowing a fast determination of whether the self refresh cycle has been completed within the pause time of the memory part. U.S. Pat. No. 5,418,754 to Sakakibara describes a system in which a self refresh cycle time is purported to be directly measured at a data output pin. U.S. Pat. No. 5,299,168 to Kang proposes a semiconductor memory circuit having a refresh address test circuit for detecting whether all of the refresh addresses have been generated.
However, these prior systems do not allow an external testing device to have general access to internal signals such as {overscore (R)}Ā{overscore (S)}, {overscore (C)}Ā{overscore (S)}, or other timing signals during self refresh.
Accordingly, there remains a need for a memory device such as a DRAM that contains circuitry that allows an external testing device to have general access to internal signals of the memory device, as well as provide external control or modification of the self refresh cycle while in a test mode.